339 search results - page 61 / 68 » Hardware Synthesis for Multi-Dimensional Time |
67
Voted
DATE
1997
IEEE
15 years 4 months ago
1997
IEEE
List scheduling algorithms attempt to minimize latency under resource constraints using a priority list. We propose a new heuristic that can be used in conjunction with any priori...
103
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ICCAD
1997
IEEE
15 years 4 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
ASYNC
2001
IEEE
15 years 4 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
ASPDAC
2005
ACM
15 years 2 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
125
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DATE
2010
IEEE
14 years 11 months ago
2010
IEEE
—Model-Based Development (MBD) provides an al level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic tr...