Sciweavers

339 search results - page 65 / 68
» Hardware Synthesis for Multi-Dimensional Time
Sort
View
VTS
2007
IEEE
143views Hardware» more  VTS 2007»
15 years 6 months ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang
CODES
2003
IEEE
15 years 5 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
CASES
2003
ACM
15 years 5 months ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara
VLSID
1999
IEEE
101views VLSI» more  VLSID 1999»
15 years 4 months ago
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
Ingo Sander, Axel Jantsch
DAC
2010
ACM
15 years 4 months ago
Reducing the number of lines in reversible circuits
Reversible logic became a promising alternative to traditional circuits because of its applications e.g. in low-power design and quantum computation. As a result, design of revers...
Robert Wille, Mathias Soeken, Rolf Drechsler