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TRETS
2010
142views more  TRETS 2010»
14 years 10 months ago
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...
John Curreri, Seth Koehler, Alan D. George, Brian ...
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
15 years 6 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
108
Voted
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 5 months ago
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, Ting...
ISPD
1998
ACM
89views Hardware» more  ISPD 1998»
15 years 4 months ago
Filling and slotting: analysis and algorithms
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Huij...
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
15 years 9 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah