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» Hardware Synthesis from C C Models
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DATE
2004
IEEE
181views Hardware» more  DATE 2004»
15 years 1 months ago
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based...
Manuel Hohenauer, Hanno Scharwächter, Kingshu...
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
15 years 2 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
DAC
2008
ACM
15 years 10 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...
IESS
2007
Springer
92views Hardware» more  IESS 2007»
15 years 3 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer