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» Hardware Synthesis of Parallel Machines from SystemC
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ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
ISCA
1989
IEEE
1033views Hardware» more  ISCA 1989»
15 years 3 months ago
Can Dataflow Subsume von Neumann Computing?
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
Rishiyur S. Nikhil
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
15 years 8 months ago
System-level power estimation using an on-chip bus performance monitoring unit
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehy...
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FCCM
2006
IEEE
101views VLSI» more  FCCM 2006»
15 years 5 months ago
A Type Architecture for Hybrid Micro-Parallel Computers
Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequenti...
Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
DSD
2009
IEEE
95views Hardware» more  DSD 2009»
15 years 6 months ago
The Parallel Sieve Method for a Virus Scanning Engine
This paper shows a new architecture for a virus scanning system, which is different from that of an intrusion detection system. The proposed method uses two-stage matching: In the...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...