186 search results - page 32 / 38 » Hardware Synthesis of Parallel Machines from SystemC |
141
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CISSE
2008
Springer
15 years 4 months ago
2008
Springer
SRI International's IraqComm system performs bidirectional speech-to-speech machine translation between English and Iraqi Arabic in the domains of force protection, municipal ...
133
Voted
DSN
2007
IEEE
15 years 8 months ago
2007
IEEE
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
ISCA
1997
IEEE
15 years 6 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
127
Voted
HPCA
2004
IEEE
16 years 2 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
142
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SPAA
2009
ACM
16 years 2 months ago
2009
ACM
Thread-level speculation (TLS) is a technique that allows parts of a sequential program to be executed in parallel. TLS ensures the parallel program's behaviour remains true ...