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» Hardware Task Scheduling for Partially Reconfigurable FPGAs
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SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
15 years 3 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 3 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
WCE
2007
14 years 11 months ago
High-Performance Multigrid Solvers in Reconfigurable Hardware
—Partial Differential Equations (PDEs) play an essential role in modeling real world problems. The broad field of modeling such systems has drawn the researchers’ attention for...
Safaa J. Kasbah, Issam W. Damaj
IPPS
2006
IEEE
15 years 4 months ago
2D defragmentation heuristics for hardware multitasking on reconfigurable devices
This paper focuses on the fragmentation problem produced in 2D run-time reconfigurable FPGAs when hardware multitasking management is considered. Though allocation heuristics can ...
Julio Septién, Hortensia Mecha, Daniel Mozo...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
15 years 3 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...