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» Hardware Task Scheduling for Partially Reconfigurable FPGAs
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FPL
2000
Springer
116views Hardware» more  FPL 2000»
15 years 2 months ago
FPGA Implementation of a Prototype WDM On-Line Scheduler
Message sequencing and channel assignment are two important aspects to consider in optimizing the performance of Wavelength Division Multiplexing (WDM) networks. A scheduling techn...
Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidz...
PPL
2008
144views more  PPL 2008»
14 years 10 months ago
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
Konstantinos Tatas, Costas Kyriacou, Paraskevas Ev...
FPL
2005
Springer
140views Hardware» more  FPL 2005»
15 years 3 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
15 years 2 months ago
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
Dirk Koch, Christian Haubelt, Jürgen Teich
FCCM
2008
IEEE
133views VLSI» more  FCCM 2008»
15 years 4 months ago
Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration
This paper presents a proto-type autonomous signal processing system on a chip. The system is architected such that high performance digital signal processing occurs in the FPGA...
Matthew French, Erik Anderson, Dong-In Kang