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» Hardware Task Scheduling for Partially Reconfigurable FPGAs
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IPPS
2006
IEEE
15 years 4 months ago
Dedicated module access in dynamically reconfigurable systems
Modern FPGAs, such as the Xilinx Virtex-II Series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) du...
Jens Hagemeyer, Boris Kettelhoit, Mario Porrmann
74
Voted
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
15 years 4 months ago
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems
To get efficient HW management in 2D Reconfigurable Systems, heuristics are needed to select the best place to locate each arriving task. We propose a technique that locates the ta...
Jesús Tabero, Julio Septién, Hortens...
CODES
2010
IEEE
14 years 7 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...
MAM
2007
157views more  MAM 2007»
14 years 10 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
15 years 5 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...