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» Hardware Task Scheduling for Partially Reconfigurable FPGAs
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TVLSI
2008
187views more  TVLSI 2008»
14 years 10 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
FPL
1997
Springer
78views Hardware» more  FPL 1997»
15 years 2 months ago
Run-time compaction of FPGA designs
Controllers for dynamically recon gurable FPGAs that are capable of supporting multiple independent tasks simultaneously need to be able to place designs at run{time when the seque...
Oliver Diessel, Hossam A. ElGindy
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 4 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...
CODES
2007
IEEE
15 years 2 months ago
Energy efficient co-scheduling in dynamically reconfigurable systems
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 5 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...