101 search results - page 17 / 21 » Hardware Task Scheduling for Partially Reconfigurable FPGAs |
114
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DELTA
2008
IEEE
15 years 6 months ago
2008
IEEE
Scheduling of concurrent processors in a real-time image processing system on FPGA (Field programmable gate array) hardware is a not a trivial task. We propose a number of graphic...
104
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ESTIMEDIA
2003
Springer
15 years 5 months ago
2003
Springer
Current multimedia applications are characterized by highly dynamic and non-deterministic behavior as well as high-performance requirements. In addition, portable devices demand a...
FPL
2007
Springer
15 years 6 months ago
2007
Springer
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
113
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ERSA
2007
15 years 1 months ago
2007
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
ASPDAC
2008
ACM
15 years 2 months ago
2008
ACM
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...