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» Hardware Task Scheduling for Partially Reconfigurable FPGAs
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IEEEPACT
2006
IEEE
15 years 4 months ago
Prematerialization: reducing register pressure for free
Modern compiler transformations that eliminate redundant computations or reorder instructions, such as partial redundancy elimination and instruction scheduling, are very effectiv...
Ivan D. Baev, Richard E. Hank, David H. Gross
FCCM
2002
IEEE
127views VLSI» more  FCCM 2002»
15 years 3 months ago
Hardware-Assisted Fast Routing
To fully realize the benefits of partial and rapid reconfiguration of field-programmable devices, we often need to dynamically schedule computing tasks and generate instance-sp...
André DeHon, Randy Huang, John Wawrzynek
FPL
2009
Springer
129views Hardware» more  FPL 2009»
15 years 3 months ago
Self-organizing multi-cue fusion for FPGA-based embedded imaging
Self-organization is a natural concept that helps complex systems to adapt themselves autonomically to their environment. In this paper, we present a self-organizing framework for...
Stefan Wildermann, Gregor Walla, Tobias Ziermann, ...
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
15 years 4 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
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CSE
2009
IEEE
15 years 2 months ago
Real Time Rectification for Stereo Correspondence
Duplicating the full dynamic capabilities of the human eye-brain combination is a difficult task but an important goal because of the wide application that a system which can acqu...
Khurram Jawed, John Morris, Tariq Khan, Georgy L. ...