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ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
14 years 11 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
SIGMETRICS
2010
ACM
201views Hardware» more  SIGMETRICS 2010»
15 years 2 months ago
Transparent, lightweight application execution replay on commodity multiprocessor operating systems
We present S, the first system to provide transparent, lowoverhead application record-replay and the ability to go live from replayed execution. S i...
Oren Laadan, Nicolas Viennot, Jason Nieh
ISCA
2009
IEEE
180views Hardware» more  ISCA 2009»
15 years 4 months ago
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zh...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 2 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
DEXAW
1997
IEEE
86views Database» more  DEXAW 1997»
15 years 1 months ago
Log-Only Temporal Object Storage
As main memory capacity increases, more of the database read requests will be satis ed from the bu er system. Consequently, the amount of disk write operations relative to disk re...
Kjetil Nørvåg, Kjell Bratbergsengen