213 search results - page 36 / 43 » Hardware Transactional Memory with Operating System Support,... |
ICS
2004
Tsinghua U.
15 years 2 months ago
2004
Tsinghua U.
Given the scale of massively parallel systems, occurrence of faults is no longer an exception but a regular event. Periodic checkpointing is becoming increasingly important in the...
SIGGRAPH
2000
ACM
15 years 1 months ago
2000
ACM
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
IWMM
2000
Springer
15 years 1 months ago
2000
Springer
The IA-64, Intel's 64-bit instruction set architecture, exhibits a number of interesting architectural features. Here we consider those features as they relate to supporting ...
CF
2006
ACM
15 years 3 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...