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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 10 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
MICRO
2008
IEEE
109views Hardware» more  MICRO 2008»
15 years 6 months ago
Dependence-aware transactional memory for increased concurrency
—Transactional memory (TM) is a promising paradigm for helping programmers take advantage of emerging multicore platforms. Though they perform well under low contention, hardware...
Hany E. Ramadan, Christopher J. Rossbach, Emmett W...
MICRO
2008
IEEE
162views Hardware» more  MICRO 2008»
14 years 11 months ago
MetaTM/TxLinux: Transactional Memory for an Operating System
This paper quantifies the effect of architectural design decisions on the performance of TxLinux. TxLinux is a Linux kernel modified to use transactions in place of locking primit...
Hany E. Ramadan, Christopher J. Rossbach, Donald E...
VEE
2012
ACM
252views Virtualization» more  VEE 2012»
13 years 7 months ago
libdft: practical dynamic data flow tracking for commodity systems
Dynamic data flow tracking (DFT) deals with tagging and tracking data of interest as they propagate during program execution. DFT has been repeatedly implemented by a variety of ...
Vasileios P. Kemerlis, Georgios Portokalidis, Kang...
FPL
2010
Springer
267views Hardware» more  FPL 2010»
14 years 9 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch