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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 5 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
CHES
2006
Springer
158views Cryptology» more  CHES 2006»
15 years 3 months ago
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrolle...
Manuel Koschuch, Joachim Lechner, Andreas Weitzer,...
84
Voted
ICC
2007
IEEE
127views Communications» more  ICC 2007»
15 years 6 months ago
A Memory Unit for Priority Management in IPSec Accelerators
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at d...
Luigi Dadda, Alberto Ferrante, Marco Macchetti
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
14 years 9 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
DATE
2007
IEEE
174views Hardware» more  DATE 2007»
15 years 6 months ago
ATLAS: a chip-multiprocessor with transactional memory support
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded appli...
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy T...