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ICECCS
2010
IEEE
196views Hardware» more  ICECCS 2010»
14 years 12 months ago
Implementing and Evaluating a Model Checker for Transactional Memory Systems
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
CF
2009
ACM
15 years 6 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt
ICCD
2008
IEEE
126views Hardware» more  ICCD 2008»
15 years 6 months ago
Accelerating search and recognition with a TCAM functional unit
Abstract— World data is increasing rapidly, doubling almost every three years[1][2]. To comprehend and use this data effectively, search and recognition (SR) applications will de...
Atif Hashmi, Mikko Lipasti
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
15 years 6 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
CACM
2011
125views more  CACM 2011»
14 years 6 months ago
Sora: high-performance software radio using general-purpose multi-core processors
This paper presents Sora, a fully programmable software radio platform on commodity PC architectures. Sora combines the performance and fidelity of hardware SDR platforms with th...
Kun Tan, He Liu, Jiansong Zhang, Yongguang Zhang, ...