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LCTRTS
2000
Springer
15 years 1 months ago
Reordering Memory Bus Transactions for Reduced Power Consumption
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
Bruce R. Childers, Tarun Nakra
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
15 years 1 months ago
Transactional Memory: Architectural Support for Lock-Free Data Structures
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
Maurice Herlihy, J. Eliot B. Moss
75
Voted
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
15 years 6 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
CF
2007
ACM
15 years 1 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
ICNC
2005
Springer
15 years 3 months ago
Parallel Genetic Algorithms on Programmable Graphics Hardware
Abstract. Parallel genetic algorithms are usually implemented on parallel machines or distributed systems. This paper describes how finegrained parallel genetic algorithms can be ...
Qizhi Yu, Chongcheng Chen, Zhigeng Pan