48 search results - page 5 / 10 » Hardware architecture design of an H.264 AVC video codec |
VTC
2010
IEEE
14 years 7 months ago
2010
IEEE
— In this contribution we propose a robust H.264 coded wireless video transmission scheme using iteratively decoded self-concatenated convolutional coding (SECCC). The proposed S...
70
Voted
DSD
2007
IEEE
15 years 3 months ago
2007
IEEE
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...
105
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ICMCS
2006
IEEE
15 years 3 months ago
2006
IEEE
We propose a high performance architecture for fractional motion estimation and Lagrange mode decision in H.264/AVC. Instead of time-consuming fractional-pixel interpolation and s...
106
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AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is d...
VLSISP
2011
14 years 4 months ago
2011
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...