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» Hardware architecture design of an H.264 AVC video codec
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DSD
2007
IEEE
164views Hardware» more  DSD 2007»
15 years 3 months ago
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10...
Serkan Oktem, Ilker Hamzaoglu
73
Voted
CODES
2005
IEEE
15 years 3 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
ICASSP
2011
IEEE
14 years 1 months ago
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
Vivienne Sze, Anantha P. Chandrakasan
SAMOS
2009
Springer
15 years 2 months ago
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems...
Yahya Jan, Lech Józwiak
ASPDAC
2006
ACM
124views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Functional modeling techniques for efficient SW code generation of video codec applications
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya