48 search results - page 7 / 10 » Hardware architecture design of an H.264 AVC video codec |
ISPASS
2007
IEEE
15 years 6 months ago
2007
IEEE
—Although SIMD extensions are a cost effective way to exploit the data level parallelism present in most media applications, we will show that they had have a very limited memory...
ISPAN
2009
IEEE
15 years 6 months ago
2009
IEEE
—In this paper, we present a design architecture of implementing a ”Vector Bank” into video encoder system, namely, an H.264 encoder, in order to detect and analyze the movin...
94
Voted
VLSISP
2008
14 years 11 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
99
Voted
ICIP
2004
IEEE
16 years 1 months ago
2004
IEEE
To leave the maximum flexibility in encoder to optimize the trade-off between coding performance and complexity, in video coding standards such as H.264/AVC [1], H.263 [2] and MPE...
96
Voted
VLSISP
2008
14 years 11 months ago
2008
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...