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» Hardware architecture design of an H.264 AVC video codec
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DAC
2006
ACM
15 years 3 months ago
Buffer memory optimization for video codec application modeled in Simulink
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Ami...
TCSV
2008
129views more  TCSV 2008»
14 years 9 months ago
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine
Since motion-compensated temporal filtering (MCTF) becomes an important temporal prediction scheme in video coding algorithms, this paper presents an efficient temporal prediction ...
Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching...
IWCMC
2009
ACM
15 years 4 months ago
Adaptive video streaming over a mobile network with TCP-friendly rate control
This paper investigates the performance of TCP-Friendly Rate Control (TFRC) to control the transmission rate of scalable video streams when used in a mobile network. The streams a...
Ktawut Tappayuthpijarn, Günther Liebl, Thomas...
DAC
2007
ACM
15 years 10 months ago
RISPP: Rotating Instruction Set Processing Platform
Adaptation in embedded processing is key in order to address efficiency. The concept of extensible embedded processors works well if a few a-priori known hot spots exist. However,...
Jörg Henkel, Lars Bauer, Muhammad Shafique, S...
88
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ASAP
2003
IEEE
113views Hardware» more  ASAP 2003»
15 years 2 months ago
A VLSI Architecture for Advanced Video Coding Motion Estimation
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in area of variable block searching motion est...
Swee Yeow, John V. McCanny