1077 search results - page 114 / 216 » Hardware code generation from dataflow programs |
111
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
115
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TCAD
2008
15 years 1 months ago
2008
Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge ...
124
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CC
1999
Springer
15 years 6 months ago
1999
Springer
In processors that do not support floating-point instructions, using fixed-point arithmetic instead of floating-point emulation trades off computation accuracy for execution spe...
HIPEAC
2010
Springer
15 years 3 months ago
2010
Springer
We present Offload, a programming model for offloading parts of a C++ application to run on accelerator cores in a heterogeneous multicore system. Code to be offloaded is enclosed ...
163
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FPL
2006
Springer
15 years 5 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...