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    » Hardware code generation from dataflow programs
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    ICPPW
    2006
    IEEE
    90views Distributed And Parallel Com...» more  ICPPW 2006»
    Multidimensional Dataflow-based Parallelization for Multimedia Instruction Set Extensions
    15 years 3 months ago
    Multidimensional Dataflow-based Parallelization for Multimedia Instruction Set Extensions
    Download  www.ece.gatech.edu
    In retargeting loop-based code for multimedia instruction set extensions, a critical issue is that vector data types of mixed precision within a loop body complicate the paralleli...
    Lewis B. Baumstark Jr., Linda M. Wills
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    MICRO
    2003
    IEEE
    135views Hardware» more  MICRO 2003»
    Generational Cache Management of Code Traces in Dynamic Optimization Systems
    15 years 2 months ago
    Generational Cache Management of Code Traces in Dynamic Optimization Systems
    Download  www.microarch.org
    A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...
    Kim M. Hazelwood, Michael D. Smith
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    ENTCS
    2008
    139views more  ENTCS 2008»
    Pervasive Compiler Verification - From Verified Programs to Verified Systems
    14 years 9 months ago
    Pervasive Compiler Verification - From Verified Programs to Verified Systems
    Download  www-ti.informatik.uni-tuebingen.de
    We report in this paper on the formal verification of a simple compiler for the C-like programming language C0. The compiler correctness proof meets the special requirements of pe...
    Dirk Leinenbach, Elena Petrova
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    ICCV
    1998
    IEEE
    464views Computer Vision» more  ICCV 1998»
    Automatic Generation of Robot Program Code: Learning from Perceptual Data
    15 years 11 months ago
    Automatic Generation of Robot Program Code: Learning from Perceptual Data
    Download  www.cse.psu.edu
    Mohammed Yeasin, Subhasis Chaudhuri
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    JUCS
    2000
    120views more  JUCS 2000»
    Execution and Cache Performance of the Scheduled Dataflow Architecture
    14 years 9 months ago
    Execution and Cache Performance of the Scheduled Dataflow Architecture
    Download  www.dii.unisi.it
    : This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
    Krishna M. Kavi, Joseph Arul, Roberto Giorgi
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