Sciweavers

1077 search results - page 153 / 216
» Hardware code generation from dataflow programs
Sort
View
CAV
2008
Springer
131views Hardware» more  CAV 2008»
15 years 3 months ago
Validating High-Level Synthesis
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
139
Voted
APSCC
2006
IEEE
15 years 5 months ago
A Model-Driven Aspect Framework for Grid Service Development
Service-Oriented Architecture (SOA) plays an important role in the next generation computing models for scientific and commercial applications. But difficulties in the development...
WenJun Li, ChuWei Huang, QiangChao Chen, Hui Bian
ICS
2004
Tsinghua U.
15 years 7 months ago
Evaluating support for global address space languages on the Cray X1
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
Christian Bell, Wei-Yu Chen, Dan Bonachea, Katheri...
CODES
2008
IEEE
15 years 3 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 5 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...