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CODES
2008
IEEE
15 years 3 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
FTCS
1998
144views more  FTCS 1998»
15 years 3 months ago
Improving Software Robustness with Dependability Cases
Programs fail mainly for two reasons: logic errors in the code, and exception failures. Exception failures can account for up to 2/3 of system crashes [6], hence are worthy of ser...
Roy A. Maxion, Robert T. Olszewski
CADE
2000
Springer
15 years 6 months ago
Machine Instruction Syntax and Semantics in Higher Order Logic
Abstract. Proof-carrying code and other applications in computer security require machine-checkable proofs of properties of machine-language programs. These in turn require axioms ...
Neophytos G. Michael, Andrew W. Appel
150
Voted
CODES
2009
IEEE
15 years 8 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
141
Voted
EGH
2010
Springer
14 years 11 months ago
AnySL: efficient and portable shading for ray tracing
While a number of different shading languages have been developed, their efficient integration into an existing renderer is notoriously difficult, often boiling down to implementi...
Ralf Karrenberg, Dmitri Rubinstein, Philipp Slusal...