1077 search results - page 160 / 216 » Hardware code generation from dataflow programs |
121
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ISCA
2010
IEEE
15 years 6 months ago
2010
IEEE
Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the se...
105
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LCPC
2000
Springer
15 years 5 months ago
2000
Springer
In translating HPF programs, a compiler has to generate local iteration and communication sets. Apart from local enumeration, local storage compression is an issue, because in HPF ...
126
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MICRO
2009
IEEE
15 years 8 months ago
2009
IEEE
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
114
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CCS
2009
ACM
16 years 2 months ago
2009
ACM
Inlined Reference Monitor (IRM) is an established enforcement mechanism for history-based access control policies. IRM enforcement injects monitoring code into the binary of an un...
71
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ISCA
1997
IEEE
15 years 5 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....