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» Hardware code generation from dataflow programs
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EMSOFT
2009
Springer
15 years 3 months ago
Modular static scheduling of synchronous data-flow networks: an efficient symbolic representation
This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flow...
Marc Pouzet, Pascal Raymond
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 8 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
POPL
2009
ACM
16 years 9 days ago
Automatic modular abstractions for linear constraints
c Modular Abstractions for Linear Constraints David Monniaux VERIMAG June 27, 2008 se a method for automatically generating abstract transformers for static by abstract interpreta...
David Monniaux
ASPLOS
2008
ACM
15 years 1 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
DATE
2009
IEEE
176views Hardware» more  DATE 2009»
15 years 6 months ago
Automated synthesis of streaming C applications to process networks in hardware
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
Sven van Haastregt, Bart Kienhuis