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» Hardware code generation from dataflow programs
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EWC
2006
61views more  EWC 2006»
15 years 1 months ago
Embarrassingly parallel mesh refinement by edge subdivision
We have previously proposed a new technique for the communication-free adaptive refinement of tetrahedral meshes that works for all configurations. Implementations of the scheme mu...
David C. Thompson, Philippe P. Pébay
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
15 years 8 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 6 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
PPPJ
2009
ACM
15 years 8 months ago
Automatic parallelization for graphics processing units
Accelerated graphics cards, or Graphics Processing Units (GPUs), have become ubiquitous in recent years. On the right kinds of problems, GPUs greatly surpass CPUs in terms of raw ...
Alan Leung, Ondrej Lhoták, Ghulam Lashari
CODES
2006
IEEE
15 years 7 months ago
Resource virtualization in real-time CORBA middleware
Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more and consistent view of those resources is presente...
Christopher D. Gill