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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 5 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
SIGMETRICS
2010
ACM
145views Hardware» more  SIGMETRICS 2010»
14 years 8 months ago
Towards architecture independent metrics for multicore performance analysis
The prevalence of multicore architectures has made the performance analysis of multithreaded applications an intriguing area of inquiry. An understanding of locality effects and c...
Milind Kulkarni, Vijay S. Pai, Derek L. Schuff
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
15 years 10 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
ACSD
2003
IEEE
125views Hardware» more  ACSD 2003»
15 years 7 months ago
Modelling a Secure, Mobile, and Transactional System with CO-OPN
Modelling complex concurrent systems is often difficult and error-prone, in particular when new concepts coming from advanced practical applications are considered. These new appl...
Didier Buchs, Stanislav Chachkov, David Hurzeler
MICRO
2003
IEEE
100views Hardware» more  MICRO 2003»
15 years 6 months ago
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...