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» Hardware code generation from dataflow programs
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ASPDAC
2000
ACM
120views Hardware» more  ASPDAC 2000»
15 years 4 months ago
Data memory minimization by sharing large size buffers
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
Hyunok Oh, Soonhoi Ha
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 6 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
DATE
2008
IEEE
91views Hardware» more  DATE 2008»
15 years 6 months ago
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams
We present several methods to generate modular code from synchronous hierarchical block diagrams. Modularity means code is generated for a given macro (i.e., composite) block inde...
Roberto Lublinerman, Stavros Tripakis
CC
2009
Springer
106views System Software» more  CC 2009»
15 years 6 months ago
Blind Optimization for Exploiting Hardware Features
Software systems typically exploit only a small fraction of the realizable performance from the underlying microprocessors. While there has been much work on hardware-aware optimiz...
Dan Knights, Todd Mytkowicz, Peter F. Sweeney, Mic...
EUROSYS
2010
ACM
15 years 5 months ago
PUSH: A Dataflow Shell
The deluge of huge data sets such as those provided by sensor networks, online transactions, and the web provide exciting opportunities for data analysis. The scale of the data ...
Noah Evans, Eric Van Hensbergen