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» Hardware code generation from dataflow programs
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CODES
2006
IEEE
15 years 3 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
SPE
1998
129views more  SPE 1998»
15 years 1 months ago
Timing Trials, or the Trials of Timing: Experiments with Scripting and User-Interface Languages
This paper describes some basic experiments to see how fast various popular scripting and user-interface languages run on a spectrum of representative tasks. We found enormous var...
Brian W. Kernighan, Christopher J. Van Wyk
ICS
2009
Tsinghua U.
15 years 8 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
TSE
2008
107views more  TSE 2008»
15 years 1 months ago
Interface Grammars for Modular Software Model Checking
We propose an interface specification language based on grammars for modular software model checking. In our interface specification language, component interfaces are specified a...
Graham Hughes, Tevfik Bultan
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 5 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...