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» Hardware code generation from dataflow programs
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CC
2007
Springer
15 years 7 months ago
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung...
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
15 years 7 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
IPPS
2005
IEEE
15 years 7 months ago
COTS Clusters vs. the Earth Simulator: An Application Study Using IMPACT-3D
In 2002, Japan announced the Earth Simulator—a supercomputer based on low-volume vector processors and a custom network—and reported that computational scientists had used it ...
Daniel G. Chavarría-Miranda, Guohua Jin, Jo...
IPPS
1999
IEEE
15 years 5 months ago
High Performance Computing for the Masses
Abstract. Recent advances in software and hardware for clustered computing have allowed scientists and computing specialists to take advantage of commodity processors in solving ch...
Mark J. Clement, Quinn Snell, Glenn Judd
PARCO
2003
15 years 2 months ago
Cache Memory Behavior of Advanced PDE Solvers
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
Dan Wallin, Henrik Johansson, Sverker Holmgren