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» Hardware code generation from dataflow programs
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TPHOL
2009
IEEE
15 years 8 months ago
A Better x86 Memory Model: x86-TSO
Abstract. Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory mode...
Scott Owens, Susmit Sarkar, Peter Sewell
IEEEPACT
2007
IEEE
15 years 7 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
CACM
2010
179views more  CACM 2010»
15 years 1 months ago
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Exploiting the multiprocessors that have recently become ubiquitous requires high-performance and reliable concurrent systems code, for concurrent data structures, operating syste...
Peter Sewell, Susmit Sarkar, Scott Owens, Francesc...
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
15 years 7 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
GTTSE
2007
Springer
15 years 7 months ago
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
With the increase of amount of transistors which can be contained on a chip and the constant expectation for more sophisticated applications, the design of Systems-on-Chip (SoC) is...
Éric Piel, Philippe Marquet, Jean-Luc Dekey...