Sciweavers

1077 search results - page 25 / 216
» Hardware code generation from dataflow programs
Sort
View
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
15 years 4 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...
CASES
2008
ACM
15 years 1 months ago
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
Hoseok Chang, Wonyong Sung
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 4 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick
ISSS
1995
IEEE
96views Hardware» more  ISSS 1995»
15 years 3 months ago
Time-constrained code compaction for DSPs
{DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code gener...
Rainer Leupers, Peter Marwedel
ICSE
2009
IEEE-ACM
16 years 16 days ago
Equality and hashing for (almost) free: Generating implementations from abstraction functions
ng Implementations from Abstraction Functions Derek Rayside, Zev Benjamin, Rishabh Singh, Joseph P. Near, Aleksandar Milicevic and Daniel Jackson Computer Science and Artificial In...
Derek Rayside, Zev Benjamin, Rishabh Singh, Joseph...