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» Hardware code generation from dataflow programs
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HPCA
2009
IEEE
16 years 2 months ago
Eliminating microarchitectural dependency from Architectural Vulnerability
The Architectural Vulnerability Factor (AVF) of a hardware structure is the probability that a fault in the structure will affect the output of a program. AVF captures both microa...
Vilas Sridharan, David R. Kaeli
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 3 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
ICALP
2001
Springer
15 years 6 months ago
Minimal Tail-Biting Trellises for Certain Cyclic Block Codes Are Easy to Construct
We give simple algorithms for the construction of generator matrices for minimal tail-biting trellises for a powerful and practical subclass of the linear cyclic codes, from which ...
Priti Shankar, P. N. A. Kumar, Harmeet Singh, B. S...
DAC
2008
ACM
15 years 3 months ago
Protecting bus-based hardware IP by secret sharing
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
CASES
2005
ACM
15 years 3 months ago
Anomalous path detection with hardware support
Embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have b...
Tao Zhang, Xiaotong Zhuang, Santosh Pande, Wenke L...