Sciweavers

1077 search results - page 53 / 216
» Hardware code generation from dataflow programs
Sort
View
ENGL
2008
100views more  ENGL 2008»
15 years 1 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid
151
Voted
FDL
2004
IEEE
15 years 5 months ago
A Functional Programming Framework of Heterogeneous Model of Computation for System Design
System-on-Chip (SOC) and other complex distributed hardware/software systems contain heterogeneous components such as DSPs, micro-controllers, application specific logic etc., whi...
Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shu...
CODES
2007
IEEE
15 years 8 months ago
Ensuring secure program execution in multiprocessor embedded systems: a case study
Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered sec...
Krutartha Patel, Sridevan Parameswaran, Seng Lin S...
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
15 years 3 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
EUROCAST
2007
Springer
122views Hardware» more  EUROCAST 2007»
15 years 5 months ago
Generation of Indexes for Compiling Efficient Parsers from Formal Specifications
abstract Parsing schemata [4] provide a formal, simple and uniform way to describe, analyze and compare different parsing algorithms. The notion of a parsing schema comes from cons...
Carlos Gómez-Rodríguez, Miguel A. Al...