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» Hardware code generation from dataflow programs
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DAC
1997
ACM
15 years 5 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
FPL
2008
Springer
150views Hardware» more  FPL 2008»
15 years 3 months ago
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computat...
Betul Buyukkurt, Walid A. Najjar
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 5 months ago
Control generation for embedded systems based on composition of modal processes
In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
CGO
2005
IEEE
15 years 7 months ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
CASES
2006
ACM
15 years 5 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean