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» Hardware design experiences in ZebraNet
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DAC
2006
ACM
15 years 10 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
ICCAD
2005
IEEE
94views Hardware» more  ICCAD 2005»
15 years 6 months ago
Post-placement voltage island generation under performance requirement
High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is prop...
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wan...
ICCAD
2002
IEEE
117views Hardware» more  ICCAD 2002»
15 years 6 months ago
An energy-conscious algorithm for memory port allocation
Multiport memories are extensively used in modern system designs because of the performance advantages they offer. The increased memory access throughput could lead to significan...
Preeti Ranjan Panda, Lakshmikantam Chitturi
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
15 years 4 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
CODES
2007
IEEE
15 years 4 months ago
Embedded software development on top of transaction-level models
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
Wolfgang Klingauf, Robert Günzel, Christian S...