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» Hardware design experiences in ZebraNet
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DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
15 years 4 months ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch
ETS
2007
IEEE
110views Hardware» more  ETS 2007»
15 years 4 months ago
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
— A novel statistical learning algorithm is proposed to accurately analyze volume diagnosis results. This algorithm effectively overcomes the inherent ambiguities in logic diagno...
Huaxing Tang, Manish Sharma, Janusz Rajski, Martin...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 3 months ago
How OEMs and suppliers can face the network integration challenges
Systems integration is a major challenge in many industries. Systematic analysis of the complex integration effects, especially with respect to timing and performance, significant...
Kai Richter, Rolf Ernst
PRDC
2005
IEEE
15 years 3 months ago
On Automating Failure Mode Analysis and Enhancing its Integrity
This paper reports our experience on the development of a design-for-safety (DFS) workbench called Risk Assessment and Management Environment (RAME) for microelectronic avionics s...
Kam S. Tso, Ann T. Tai, Savio N. Chau, Leon Alkala...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 3 months ago
Verification of the RF Subsystem within Wireless LAN System Level Simulation
Today’s mobile communication systems use sophisticated signal processing to achieve high transmission rates. Therefore a high complexity in the digital system part as well as ve...
Uwe Knöchel, Thomas Markwirth, Jürgen Ha...