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ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
SIGMETRICS
2002
ACM
105views Hardware» more  SIGMETRICS 2002»
14 years 9 months ago
Modeling and analysis of dynamic coscheduling in parallel and distributed environments
Scheduling in large-scale parallel systems has been and continues to be an important and challenging research problem. Several key factors, including the increasing use of off-the...
Mark S. Squillante, Yanyong Zhang, Anand Sivasubra...
MICRO
2010
IEEE
142views Hardware» more  MICRO 2010»
14 years 7 months ago
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
Daehoon Kim, Hwanju Kim, Jaehyuk Huh
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
14 years 7 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
14 years 7 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu