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» Hardware design experiences in ZebraNet
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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 3 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
EH
2003
IEEE
136views Hardware» more  EH 2003»
15 years 3 months ago
Experimental Results in Evolutionary Fault-Recovery for Field Programmable
This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alo...
Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong,...
ICCAD
2000
IEEE
137views Hardware» more  ICCAD 2000»
15 years 2 months ago
Smart Simulation Using Collaborative Formal and Simulation Engines
computation and automatic abstraction. Second, Ketchum performs not only automatic test generation but also unreachability analysis, which enables the test generation effort to be ...
Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James ...
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
15 years 2 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
TEI
2010
ACM
170views Hardware» more  TEI 2010»
15 years 4 months ago
Swing that thing: moving to move
Swing That Thing… is a practice-based doctoral research project that examines how technology in on and around the body might be used to poeticise experience. Outcomes include a ...
Danielle Wilde