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» Hardware design experiences in ZebraNet
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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 6 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
DATE
2007
IEEE
56views Hardware» more  DATE 2007»
15 years 4 months ago
Unknown blocking scheme for low control data volume and high observability
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar
DATE
2007
IEEE
160views Hardware» more  DATE 2007»
15 years 4 months ago
FPGA-based networking systems for high data-rate and reliable in-vehicle communications
The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automot...
Sergio Saponara, Esa Petri, Marco Tonarelli, Iacop...
MICRO
2006
IEEE
103views Hardware» more  MICRO 2006»
15 years 3 months ago
NoSQ: Store-Load Communication without a Store Queue
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
Tingting Sha, Milo M. K. Martin, Amir Roth
VEE
2006
ACM
116views Virtualization» more  VEE 2006»
15 years 3 months ago
Relative factors in performance analysis of Java virtual machines
Many new Java runtime optimizations report relatively small, single-digit performance improvements. On modern virtual and actual hardware, however, the performance impact of an op...
Dayong Gu, Clark Verbrugge, Etienne M. Gagnon