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ISLPED
2009
ACM
188views Hardware» more  ISLPED 2009»
15 years 4 months ago
Transaction-based adaptive dynamic voltage scaling for interactive applications
In an interactive embedded system, special task execution patterns and scheduling constraints exist due to frequent human-computer interactions. This paper proposes a transaction-...
Xia Zhao, Yao Guo, Xiangqun Chen
ISLPED
2009
ACM
100views Hardware» more  ISLPED 2009»
15 years 4 months ago
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Post-fabrication tuning for mitigating manufacturing variability is receiving a significant attention. To reduce leakage increase involved in performance compensation by body bia...
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuya...
SIGMETRICS
2009
ACM
149views Hardware» more  SIGMETRICS 2009»
15 years 4 months ago
On the treeness of internet latency and bandwidth
Existing empirical studies of Internet structure and path properties indicate that the Internet is tree-like. This work quantifies the degree to which at least two important Inte...
Venugopalan Ramasubramanian, Dahlia Malkhi, Fabian...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
15 years 4 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 4 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...