Sciweavers

951 search results - page 133 / 191
» Hardware design experiences in ZebraNet
Sort
View
TVCG
2012
210views Hardware» more  TVCG 2012»
13 years 5 days ago
Scalable Multivariate Volume Visualization and Analysis Based on Dimension Projection and Parallel Coordinates
—In this paper, we present an effective and scalable system for multivariate volume data visualization and analysis with a novel transfer function interface design that tightly c...
Hanqi Guo, He Xiao, Xiaoru Yuan
TEI
2009
ACM
95views Hardware» more  TEI 2009»
15 years 4 months ago
Living interfaces: the intimate door lock
In this paper we introduce a new way to interact intimately with an automated system. The Intimate Door Lock investigates the psychological effects of intimate humanhuman interact...
Miriam Roy, Fabian Hemmert, Reto Wettach
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
15 years 4 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
15 years 3 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
15 years 3 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel