951 search results - page 46 / 191 » Hardware design experiences in ZebraNet |
ITC
1996
IEEE
15 years 6 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
ICCD
1994
IEEE
15 years 6 months ago
1994
IEEE
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
143
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FPGA
2008
ACM
15 years 3 months ago
2008
ACM
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
101
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ISLPED
2007
ACM
15 years 3 months ago
2007
ACM
To address the productivity bottlenecks in power analysis and optimization of modern systems, we propose to treat power as a signal and leverage the rich set of signal processing ...
124
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ETS
2000
IEEE
15 years 1 months ago
2000
IEEE
A significant opportunity presented by the availability of high-speed network access in the classroom is the ability to collaborate with remote students and mentors. To be success...