951 search results - page 93 / 191 » Hardware design experiences in ZebraNet |
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
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DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought be high for sucessfull diagnosis of analogue...
CAV
2000
Springer
15 years 2 months ago
2000
Springer
Abstract. Bounded Model Checking based on SAT methods has recently been introduced as a complementary technique to BDD-based Symbolic Model Checking. The basic idea is to search fo...