421 search results - page 43 / 85 » Hardware efficient architectures for Eigenvalue computation |
128
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VLSID
2007
IEEE
16 years 4 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
104
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DAC
2007
ACM
16 years 4 months ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
132
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VLSID
2005
IEEE
16 years 4 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
ICCAD
1996
IEEE
15 years 8 months ago
1996
IEEE
A number of methods are presentedfor highly efficient calculation of substratecurrenttransport. A three-dimensionalGreen'sFunction based substrate representation, in combinat...
145
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HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...