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» Hardware efficient architectures for Eigenvalue computation
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DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 10 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
FPL
2010
Springer
129views Hardware» more  FPL 2010»
15 years 1 months ago
FPGA Implementations of the Round Two SHA-3 Candidates
Abstract--The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper present...
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilt...
ERSA
2010
172views Hardware» more  ERSA 2010»
15 years 1 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
FPL
2004
Springer
144views Hardware» more  FPL 2004»
15 years 7 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
SBACPAD
2003
IEEE
138views Hardware» more  SBACPAD 2003»
15 years 9 months ago
Finite Difference Simulations of the Navier-Stokes Equations Using Parallel Distributed Computing
 This paper discusses the implementation of a numerical algorithm for simulating incompressible fluid flows based on the finite difference method and designed for parallel compu...
João Paulo De Angeli, Andréa M. P. V...