421 search results - page 45 / 85 » Hardware efficient architectures for Eigenvalue computation |
143
click to vote
ISLPED
2003
ACM
15 years 9 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
150
click to vote
ASAP
2005
IEEE
15 years 9 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
169
click to vote
IPPS
2010
IEEE
15 years 1 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
109
click to vote
FPL
2005
Springer
15 years 9 months ago
2005
Springer
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
134
Voted
HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
This paper presents hardware and software mechanisms to enable concurrent direct network access (CDNA) by operating systems running within a virtual machine monitor. In a conventi...